Attempts to increase device integration density in microelectronic integrated circuits typically have resulted in the fabrication of smaller and smaller MOS transistors having shorter channels. Decreasing the channel length of the MOS transistors, however, degrades the punch-through characteristics and the drain induced barrier lowering (DIBL) characteristics. Due to this degradation, drain leakage current can flow through the channel even if a sub-threshold voltage is applied to the gate of the MOS transistor. This in turn increases a stand-by current of the semiconductor device that includes short channel MOS transistors. Many mechanisms have therefore been proposed in order to solve this short channel effect.
For example, proposed methods of improving the short channel effect include reducing the thickness of the gate insulating layer, and increasing the doping concentration of the channel. These methods, however, result in the variation of the threshold voltage of the MOS transistor. Accordingly, techniques recently have been developed for forming shallow source/drain regions in order to improve the short channel effect. Forming the source/drain regions too shallow, however, reduces the process margin of over etching for forming contact holes and exposing the source/drain regions. In other words, if the junction depth of the source/drain region is too shallow, it is difficult to control the over etching process for etching an interlayer insulating layer on the shallow source/drain regions.
A method of forming a MOS transistor is described in U.S. Pat. No. 5,843,826 entitled “Deep submicron MOSFET device” by Hong, which is incorporated herein by reference in its entirety. According to Hong, elevated polysilicon patterns are formed on isolation layers at both sides of an active region, and a silicon layer is grown using a selective epitaxial growth technology on the active region and the elevated polysilicon patterns. A MOS transistor then is formed on the epitaxial silicon layer using conventional methods. Accordingly, it is possible to realize elevated source/drain regions extending into the upper regions of the isolation layer. As a result, it is possible to minimize the width of the active region and to concurrently increase the over etching process margin during formation of the contact hole and exposing the source/drain region.
Selective epitaxial growth technology, however, requires very accurate process conditions. For example, surfaces of the underlying material layers, e.g., the active region and the polysilicon layer should be very clean. Thus, it is difficult to form a uniform epitaxial layer on the active region and the polysilicon pattern, in the event that contaminants such as crystal defects due to the etch damages, or native oxide layers exist on the active region or the polysilicon pattern. Thus, a pre-cleaning treatment needs to be performed prior to the epitaxial growing process, which requires very careful attention. Also, according to Hong, it is difficult to minimize the width of the isolation layer under the elevated source/drain region. Accordingly, there are limitations in increasing the integration density using the methods described in Hong.